Design Simulation and Silicon Implementation of a Very High Fidelity 24-bit Potential Decimation Filter for Sigma-Delta A/D Converters

This paper reports on results from the algorithmic design and simulation of a two-path poly-phase decimation filter with 24-bit accuracy over the frequency range from dc to approximately 16kHz. The filter is suited for very high precision data conversion applications, and has been designed for use with a fourth-order  modulator running at 4096kHz. This paper also reports on the fixed-point architectural design, comparative bit-level simulations and silicon implementation of the filter.